The minimum feature sizes of integrated circuits (ICs) have been shrinking for years. Commensurate with this size reduction, various process limitations have made IC fabrication more difficult. One area of fabrication technology in which such limitations have appeared is photolithography. Photolithography is a process used in semiconductor device fabrication to transfer a pattern from a photomask (also called reticle) to the surface of a substrate. The pattern of the photomask (“mask”) corresponds to features on one layer in an IC design. As light passes through the mask, it is refracted and scattered by the mask edges. This causes the projected image to exhibit some rounding and other optical distortion. While such effects pose relatively little difficulty in layouts with large feature sizes (e.g., layouts with critical dimensions above about 1 micron), they cannot be ignored in layouts having features smaller than about 1 micron. The problems become especially pronounced in subwavelength lithography in which features of a device design are printed that are smaller than the wavelength of light used in the photolithographic process.
Lithography design rules define the parameters for controlling how a particular IC is designed and fabricated using a particular process technology. Examples of such parameters include minimum and maximum feature sizes and spacing. The design rules also include process latitude specifications that are defined to guarantee manufacturability of each processing step. For example, in the photolithography processing step, a minimum combined depth of focus for a given exposure latitude for all features is specified to guarantee printability of layout patterns of a given layer in the design layout. The process latitude specifications define lithography process windows for many of the parameters in the design rules. Process windows represent the amount of allowed critical dimension (CD) and overlay variation of features during manufacturing. As design rules controlling the printing of such features continue to shrink, so too are lithography process windows. This affects the focus and exposure latitude within which a desired feature can be printed within design rule specification.
Resolution enhancement techniques such as optical proximity correction (OPC), phase-shift masks and double exposure are used to enable pattern printing in subwavelength lithography. Optical proximity correction involves adding dark regions to and/or subtracting dark regions from a mask design at locations chosen to overcome the distorting effects of diffraction and scattering. Typically, OPC is performed on a digital representation of a desired IC pattern. The digital pattern is evaluated with software to identify regions where optical distortion will result, and a digital representation of the mask design is modified to create an optically corrected or OPC mask.
Given the many different feature types, sizes, densities and configurations of layout patterns, however, some of the patterns in the layout will not meet the process latitude specifications even with OPC and would tend to reduce a common process window and yield of the design layer. Because of proximity effects during printing, the effect on each feature by neighboring shapes ripples through the design. The process window simulation typically attempts to calculate all these rippling effects through brute force and then identify areas in the design layout that result in very small or non-compliant process windows. Given the size of data for a given design, it is prohibitively expensive to analyze the process window compliance of the entire design layer. For example, a typical 10 mm×10 mm design layout may comprise millions of features. Generally, the computational time required to analyze process window compliance of a design layer is the square of the area to be processed.
If the design layout calls for a change in any of the optical parameters (e.g., dose or focus), the process window calculations have to be performed over again. If it takes one day at one dose and focus setting to perform the calculation, for example, and the design layout calls for a change in dose or focus, many days may be needed to complete the calculations. The time to perform the calculation may be reduced but requires a massive investment in hardware.
Accordingly, there is a need for an improved method for analyzing process window compliance of an IC design. The present invention addresses such a need.